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Functional Coverage Interview Questions: Bins, Crosses, and Unreachable Goals
Practice functional coverage interview questions with bin goals, cross denominators, accepted-event sampling, unreachable-goal triage, and reviewed exclusions.
A regression reports 100% coverage while the scoreboard still finds corrupted data. Another regression stops at 85.7%, and someone proposes excluding the remaining bin. Neither percentage answers whether the design meets its requirements. Functional coverage interview questions test whether you can explain the goals behind the number, the observation that hits each goal, and the evidence needed to change the denominator.
The thesis is that coverage is evidence against a defined requirement model, not a correctness certificate. Begin with a protocol contract, sample what actually happened, and diagnose each missing goal before changing the model.
Evidence boundary: Siemens Verification Academy publications provide vendor guidance; a named Siemens expert's forum explanation is labeled separately. The protocol, percentages, ledgers, and triage recommendations below are original exercises and engineering inference. No candidate reports or employer-specific interview frequencies are claimed. Practice the requirements framing with Verification Plan for a FIFO, a Round-Robin Arbiter and a Valid/Ready Handshake.
What should a functional coverage bin represent?
Official vendor guidance: Siemens describes functional verification as checking the design requirements defined by the specification. Its coverage-model debugging paper explains that a covergroup contains coverpoints and optionally crosses, and that the coverage model itself can contain bugs. See Functional Coverage Metrics and Debugging Functional Coverage Models.
A bin should represent a meaningful observation from the verification plan. It might group a boundary value, transaction class, or state transition. Naming a variable in a coverpoint does not explain why its values are verification goals. Link the goal to a requirement and the relevant sampling condition.
Original exercise: A command interface accepts reads and writes. Length is short or long. Mode is basic or extended. The specification forbids a long write in basic mode, while all other combinations are required. These categories describe this exercise's contract; they are not a claim about a real bus standard.
Before implementing the coverage model, write down the seven legal requirements explicitly. Ask whether “long” means a transaction's requested length, accepted length, or successfully completed length. Those choices can produce different evidence even with identical stimulus.
Make the denominator reviewable: each retained or excluded goal needs a requirement rationale. One broad bin for all writes might be enough for a coarse smoke-test goal, but it cannot distinguish a tested short write from an untested long write when the specification requires both.
Sample accepted behavior instead of attempted stimulus
Original exercise: The driver offers a long extended write while valid is high. The receiver keeps ready low for three cycles and accepts on the fourth. If the coverage goal is an accepted command, the first three cycles should not hit that command bin.
A monitor can sample a stable transaction representation when valid && ready establishes acceptance under this exercise's interface contract. This is a verification-design recommendation, not a universal sampling expression for every protocol. A different bus may define acceptance or completion differently.
Sampling at the sequence generator measures attempted stimulus. Sampling at acceptance measures what reached the design's interface. Sampling at checked completion measures another boundary. All three can be useful, but they must be named so one is not mistaken for another.
Consider reset during the stall. The generator attempted a transaction, but no accepted command occurred. Counting it as accepted would hide a hole. Conversely, recording only successful completions might omit accepted transactions that exposed a failure; that is why correctness evidence and observed behavior need separate reporting.
Avoid an unexplained sampling race. A covergroup triggered at a clock edge and a monitor that updates transaction fields later in the simulation timestep can disagree about which values were observed. Define the monitor's sampling boundary and stable transaction object before trusting a count. Verify it with a short deterministic trace containing a stall, an acceptance, and a reset.
Calculate the cross denominator explicitly
Original goal ledger: Two operations multiplied by two length categories multiplied by two modes gives eight combinations. Excluding the one combination forbidden by this exercise's specification leaves seven required goals.
| Combination group | Raw goals | Required goals | Observed required goals |
|---|---|---|---|
| Reads: both lengths, both modes | 4 | 4 | 4 |
| Short writes: both modes | 2 | 2 | 2 |
| Long write in extended mode | 1 | 1 | 0 |
| Long write in basic mode | 1 | 0 | 0 |
| Total | 8 | 7 | 6 |
For equal goal weights and a hit threshold of one, this model's coverage is 6 / 7 × 100 = 85.7%. This is original requirement arithmetic, not a claim that every simulator's aggregate percentage uses this formula. Weights, hit thresholds, instance settings, and the model hierarchy can change reported aggregation.
The uncovered extended long write is still a legal required operation. Removing it would make this small model report 100%, but would also remove a requirement. That is a model change, not a test improvement.
Official vendor guidance: Siemens' cross-debugging publication discusses grouping expected combinations and analyzing related crosses to identify coverage holes. See the cover-cross analysis paper. Its guidance supports inspecting the modeled combinations rather than treating an aggregate score as self-explanatory.
Adding another dimension expands the model quickly. Crossing a transaction identifier with every operation could create thousands of goals that have no separate requirement meaning. Cross categories because their interaction matters, not simply because all signals are available in the monitor.
Does iff remove an unreachable bin?
Named vendor-expert guidance: In an October 2025 Verification Academy reply, Siemens expert Dave Rich explains that iff blocks sampling rather than bin construction. See Excluding the already defined bins. This is an identified expert explanation, not a candidate report or a substitute for the language reference and your simulator's supported version.
Original exercise: Suppose a bin requires the long extended write, but a sampling guard is false throughout the regression. The requirement did not disappear. It was never eligible to be observed. A lower hit count can reflect a broken guard rather than missing random seeds.
Separate three decisions: whether an observation is sampled, which observations map to a goal, and which goals belong in the model. In this exercise, valid && ready addresses the observation boundary. Excluding the forbidden long basic write addresses the requirement set. They solve different problems.
Use an explicitly reviewed exclusion when a combination is outside the contract. Do not hide an untested legal combination by weakening weights or changing the guard until the report looks complete. Preserve the before-and-after goal list so a reviewer can see what changed.
If writing SystemVerilog syntax in an interview, identify the language edition, tool version, and automatic-cross-bin behavior you are assuming. User-defined cross bins and remaining automatic bins can make the implementation's denominator differ from the handwritten ledger. The safe next step is to inspect the generated bin report against the intended seven goals.
Distinguish ignored behavior from illegal behavior
Engineering recommendation: Excluding a combination from the required coverage goals does not by itself provide a complete check that the design rejects it. The exercise's forbidden long basic write needs a separate correctness requirement: what should the interface or design do if that input occurs?
If an illegal_bins declaration is part of your implementation, explain the simulator's reporting behavior and how the regression treats it. Do not assume that a coverage declaration alone checks the entire temporal rejection protocol. Assertions and scoreboards can express different failure conditions and timing relationships.
For this exercise, one check could verify that an invalid request never produces a success response. Another could verify a documented error response or rejection behavior. Which is correct depends on the specification. A bin label does not choose that contract for you.
Likewise, a coverage hit for a legal write does not prove its data was correct. The monitor may have observed the accepted operation while the scoreboard detected a wrong result. Keep the coverage evidence and correctness result linked through transaction identity without allowing the hit to erase the failure.
Why is a goal unreachable?
Original triage matrix: Start with the missing extended long write from the seven-goal ledger.
| Proposed cause | Evidence to seek | Appropriate next action |
|---|---|---|
| Stimulus constraint blocks it | Constraint set and a targeted generation attempt | Repair unintended constraints or add directed stimulus |
| Driver never presents it correctly | Sequence item and interface waveform | Fix the stimulus-to-interface path |
| Receiver never accepts it | Handshake trace and documented acceptance rules | Diagnose backpressure, configuration, or design behavior |
| Monitor samples wrong fields | Accepted transaction compared with coverage input | Repair sampling or category mapping |
| Specification forbids it in this configuration | Requirement and configuration evidence | Review a configuration-specific exclusion |
| Formal analysis cannot reach it | Proof result plus assumptions and model scope | Review whether assumptions match the verification contract |
A long run without a hit establishes nonobservation; impossibility needs additional evidence. A generator constraint can also make a legal design goal unreachable from that generator, without making it unreachable in the design.
For a waiver, retain the exact goal, configuration, requirement rationale, assumptions, evidence, reviewer, and model revision. The waiver should be specific enough to revisit after a specification or configuration change. “Tool says unreachable” leaves out the conditions under which the conclusion was obtained.
A proof constrained to reset permanently asserted does not justify excluding a post-reset transaction from normal operation. Similarly, an environment assumption that prevents long commands can accidentally prove away the very behavior the plan needs to test.
Can merged coverage hide an instance gap?
Official vendor guidance: Siemens' paper on simplifying functional coverage models describes how covergroup options and instance merging affect observed results and debug visibility. See Unraveling the Complexities of Functional Coverage.
Original exercise: Two identical ports each require short and long reads. Port A observes only short reads; port B observes only long reads. A union of observations contains both categories, while neither individual port has covered both.
Whether that union is sufficient depends on the requirement. If every port must implement both behaviors, a merged total cannot replace per-instance evidence. If the goal intentionally concerns system-wide occurrence, a system-level model may be appropriate. Name the scope before comparing percentages.
Regression merging also needs compatible model versions and configurations. Six hits against yesterday's seven-goal model are not automatically comparable with six hits against today's six-goal model. Preserve the specification, configuration, model revision, and run outcomes with the report.
The arithmetic and accepted-event examples for this article were checked as small executable models. No covergroup-capable SystemVerilog simulation was executed here. These checks validate the exercise ledger, not language syntax, vendor reporting, or hardware signoff.
Five exercises to connect goals with evidence
These questions cover verification planning and evidence quality. The software and firmware exercises are included for transferable test reasoning, not as SystemVerilog language authorities.
| Question | Coverage follow-up |
|---|---|
| Verification Plan for a FIFO, a Round-Robin Arbiter and a Valid/Ready Handshake | Define sampling and legal transaction goals. |
| ASIC Verification Fundamentals Across SystemVerilog UVM CDC and Architecture | Separate stimulus, coverage, assertions, and scoreboard evidence. |
| Explain SystemVerilog verification concepts and write constraints | Diagnose whether constraints block a legal goal. |
| Validate Unit-Test Coverage and Identify Missing Scenarios | Challenge a percentage that hides an omitted requirement. |
| Build a Firmware Data Quality and Release-Feedback Framework | Preserve evidence and scope through regression review. |
Continue with the FIFO, arbiter, and handshake verification plan. Write the goal list before the covergroup, then inject one stalled transaction and one forbidden combination. Explain what should be sampled, checked, and excluded.